1. Field of the Invention
The present invention is generally related to the field of semiconductor fabrication. More particularly, the present invention is related to an improved method of fabricating contact holes, via holes or openings on a semiconductor wafer, which is suited for semiconductor processes beyond 65 nm or 45 nm.
2. Description of the Prior Art
The trend to micro-miniaturization, or the ability to fabricate semiconductor devices with feature size smaller than 65 nanometers, has presented difficulties when attempting to form contact holes (especially for high aspect ratio contact holes) in a dielectric layer to expose underlying conductive regions.
Conventionally, photoresist-mask approach and hard-mask approach are employed in the fabrication of contact or via holes on a semiconductor wafer. The aforesaid photoresist-mask approach has a shortcoming in that the 193 nm photoresist (reactive to 193 nm wavelength light) has its optical limitations in the optical lithographic process. For example, for fabricating a contact hole with line width of 65 nm, limited to optical limitation of a 180-200 nm pitch, only an in-line after development inspect critical dimension (ADICD) of about 120 nm can be achieved.
In order to increase the process window and depth of focus (DOF) of photoresist, it is necessary to decrease the thickness of the photoresist, which increases difficulty of subsequent dry etching process due to insufficient thickness of the photoresist that acts as an etching hard mask. Furthermore, The aforesaid photoresist-mask approach has drawbacks such as so-called standard wave problem and bowling profile problem.
The aforesaid hard-mask approach typically utilizes an etching hard mask containing metals or metal alloys that increases the complexity of the contact process. Besides the etching resistance of the hard mask itself, there are so many factors that are needed to take into account when using metal hard mask in the contact process. For example, the deposition temperature of the hard mask can not exceed 400° C. in order not to affect the previously formed layers such as silicide layers of a metal-oxide-semiconductor (MOS) transistor device. It is also a problem of removing the remanent metal hard mask after etching the contact hole.
In light of the above, there is a need in this industry to provide an improved method for fabricating contact holes, via holes or openings on a semiconductor wafer that does not use metal hard mask and is capable of tacking the above-mentioned difficulties and problems, and achieving the desired after etch inspection critical dimension (AEICD) and contact hole profile.